archives

An Expressive Language of Signatures

An Expressive Language of Signatures. Norman Ramsey and Kathleen Fisher and Paul Govereau. ICFP'05.

Our language includes operations for adding, renaming, and removing components; for changing the type associated with a value; for making a manifest type abstract or vice versa; and for combining two interfaces. These operations can express useful relationships among interfaces.

The authors want to help programmers express nontrivial relationships between interfaces, in order to better understand and explain the structure of complex software systems. To meet this goal they introduce new language design, with fairly rich and expressive concrete syntax.

This line of work is related to issues I wrote about. I remember Ramsey implying he is thinking about these issues in one of his web pages, and I waited to see what he would come up with. I guess this is it...

This is an important area, and I am sure there's still a lot to be done.

Leak Free Javascript Closures

I haven't read this really, but it's in the queue for such a long time I might as well pass it along...

Compiler Technology for Scalable Architectures

Seems like an interesting (if not very in-depth) read.

Our aim is to automatically generate high quality code taking advantage of the wide range of heterogeneous parallelism for Scale-Up and Scale-Out architectures. We propose "single source" compiler solutions for heterogeneous memory and computational subsystems using automatically-partitioned code and data, as well as software-managed cache for irregular data accesses. We exploit parallelism at all levels, including data and task level parallelism as well as SIMD parallelism.

One such heterogeneous platform is the Cell Broadband Engine (TM) (referred to thereafter as Cell), which includes a Power-Architecture processor and eight attached streaming processors with their own memory and DMA engines. In addition, each processor has several SIMD units that can process from 2 double-precision floating-point values up to 16 byte-values per instruction.

We propose techniques that include compiler optimizations partitioning for data and code to run on the multiple heterogeneous processor elements in the system, automatic generation of SIMD code, and other specialized optimizations for processor elements in the Cell architecture. Measurement indicates that significant speedups are achieved with a high level of support from the compiler.