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MyHDL

(via Daily Python-URL)

The key idea behind MyHDL is the use of Python generators to model hardware concurrency. Generators are best described as resumable functions. In MyHDL, generators are used in a specific way so that they become similar to always blocks in Verilog or processes in VHDL.

A hardware module is modeled as a function that returns any number of generators. This approach makes it straightforward to support features such as arbitrary hierarchy, named port association, arrays of instances, and conditional instantiation.

MyHDL is an open-source package for using Python as a hardware description and verification language. A Verilog converter is also included.

EE Times provides some background on MyHDL in this article.

By Ehud Lamm at 2006-01-26 16:53 | DSL | Python | other blogs | 11222 reads

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Verilog conversion

One of the more interesting aspects of MyHDL is the way in which conversion to Verilog is done:

The conversion does not start from source files, but from an instantiated design that has been elaborated by the Python interpreter. The converter uses the Python profiler to track the interpreter's operation and to infer the design structure and name spaces. It then selectively compiles pieces of source code for additional analysis and for conversion. This is done using the Python compiler package.

The specific implementation details sound kind of kludgy and brittle, but the overall approach is interesting and it sounds like it could be implemented much more cleanly and robustly as an abstract interpreter in PyPy via a custom ObjSpace; they're already using a variety of different ObjSpaces for e.g. type inference and flow analysis.

An overview of PyPy's ObjSpace architecture can be found here:

http://codespeak.net/pypy/dist/pypy/doc/theory.html#abstract-interpretation
http://codespeak.net/pypy/dist/pypy/doc/objspace.html

By Per Vognsen at Fri, 2006-01-27 02:36 | login or register to post comments

PyPy ObjSpace

This looks very interesting. Thanks for the link!

By Ehud Lamm at Fri, 2006-01-27 12:23 | login or register to post comments

Generators ?

Funny that, I'd have described generators as the poor man's lazy evaluation. Or as the not-so-poor man's fiber/microthread.

Still, looks interesting. How does this relate to, say, HDCaml ?

By David Teller at Fri, 2006-01-27 11:17 | login or register to post comments

Python

I'm puzzled by the insistance of HW developpers in the US for not using the real tools, i.e. VHDL and, more recently, SystemC.
The modelisation of the inherently parallel digital electronic designs is based on events and independant processes awaken by transactions on interconnected signals : Some kind of actor programming.
VHDL is not dynamic enough for being used as a 'normal' programming language but maybe SystemC ( which is based on C++ ) can yield interesting experiments in that area.
( ... but I'm not discussing the usefulness of the PyPy project, which is great )

By odanet at Sat, 2006-01-28 15:36 | login or register to post comments

VHDL is not dynamic enough

VHDL is not dynamic enough for being used as a 'normal' programming language

Just being curious: Why would anyone want to use VHDL as a normal programming language ?

By David Teller at Tue, 2006-01-31 16:16 | login or register to post comments