Seems like an interesting (if not very in-depth) read.
Our aim is to automatically generate high quality code taking advantage of the wide range of heterogeneous parallelism for Scale-Up and Scale-Out architectures. We propose "single source" compiler solutions for heterogeneous memory and computational subsystems using automatically-partitioned code and data, as well as software-managed cache for irregular data accesses. We exploit parallelism at all levels, including data and task level parallelism as well as SIMD parallelism.
One such heterogeneous platform is the Cell Broadband Engine (TM) (referred to thereafter as Cell), which includes a Power-Architecture processor and eight attached streaming processors with their own memory and DMA engines. In addition, each processor has several SIMD units that can process from 2 double-precision floating-point values up to 16 byte-values per instruction.
We propose techniques that include compiler optimizations partitioning for data and code to run on the multiple heterogeneous processor elements in the system, automatic generation of SIMD code, and other specialized optimizations for processor elements in the Cell architecture. Measurement indicates that significant speedups are achieved with a high level of support from the compiler.
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