Add "unit time delay (D)" operator to functional language with random signals instead of random vars

My current interest is the "good old theme" according to some that functional languages better match the operation of digital circuits in a "data flow" design as in behavioral VHDL, and could be used a language to describe such circuits from which the HDL is then generated. At the same time one could develop and simulate the behavior using an ordinary PC.

As many say, some imperative syntax regularly still comes in very handy even in a functional language. For instance, already if one tries to define a finite impulse response (FIR) filter and its underlying shift register, it comes to mind to make the "single assignment" in functional programming languages refer to "(random) signals" (i.e. time functions) instead of "(random) variables". A unit delay operator on such signals of a discrete time clock would then be a prominent operator in such a language. For instance, each element in the aforementioned shift register would be a one time unit delayed copy of its left neighbor, still defined with a single assignment. Only when such a delay operator is added to a functional language does the whole time dimension of signal processing open up.

I have searched the internet for ideas like this, but did not find a hit. My question is, whether idea like this have been explored before?

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unit delay operator

A good place to start in understanding what has been done along these lines would be to look into the subject of dataflow languages, for example the venerable Lucid and Lustre languages.

There are two basic

There are two basic functional branches inspired by the hardware (embedded/synchronous) approach of Esterel: Lustre/Synchrone/etc (variables get updated at the end of every step) and FRP (terms are functions of time or globally synchronized dataflow nodes). There's been a lot on both families on LtU. A particularly fun sampler is the Ptolemy project.

Good luck!

Pleas, take a look at

Pleas, take a look at ForSyDe for a general attack direction. And yes, they have pure HDL computations (combinatoric circuits) practically without any delay and computations with registers that have formal delay for one clock cycle.

My current understanding is that you have to describe netlists (coomponents and connections) first then you can express most of high-level concepts over it. The register (clock cycle delay element) becomes just another component that you have to combine with others. "IF" statement is a selector (or little more than selector).

FIR then can be created semiautomatically using "macros" - code that depends on parameter (number of FIR taps) and generate appropriate netlist.

If you haven't already...

...check out Lava

I did.

Lava is good, albeit slightly low-level.

I tried to lift level of Haskell HDLs, but didn't succeed (yet).

My best attempt is here: some stages of MIPS CPU - decoder, read and execute.

I figured out how to translate almost regular Haskell code into code over infinite lists (Hawk style), but failed to write a translator into netlists (not enough spare time).