A real time collector for reconfigurable hardware seems kinda like a nice little 'hardware' implementation.
It is thus quite a tour de force that the authors of the following paper have built a provably correct real-time collec- tor for reconfigurable hardware (field programmable gate arrays). How can this be? It turns out the FPGA setting makes the problem simpler in some ways than is the case with software GC running on stock processors. They can reasonably impose simple uniformity on the memory and its layout; they can exploit single-clock read-modify-write steps; and perhaps most importantly they have, via dual ported memory, com- pletely concurrent memory access. This all leads to one of the cleanest and per- haps most understandable implemen- tations of a concurrent GC that has ever been presented. The other prerequisites for real-time collection also follow eas- ily. It is difficult to find the right word to express the feeling I get seeing such a so- phisticated algorithmic idea reduced to such a straightforward hardware imple- mentation—“Cool!†will have to suffice. (emphasis mine)
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